173 lines
5.7 KiB
C
173 lines
5.7 KiB
C
// w2812_defs.h
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//
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// contains material from Charles Lohr, but changed by me.
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#ifndef __WS2812_I2S_DEFS_H__
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#define __WS2812_I2S_DEFS_H__
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#include <stdint.h>
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// include file from project folder
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#include "ws2812.h"
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// -----------------------------------------------------
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// Helper macro's
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#define NUM_RGB_BYTES (num_leds * 3)
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#define NUM_I2S_PIXEL_BYTES (num_leds * 3 * 4) // (#leds) * (RGB) * (4 i2s bits)
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#define NUM_I2S_PIXEL_WORDS (num_leds * 3)
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// -----------------------------------------------------
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// I2S timing parameters
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// Creates an I2S SR of 93,750 Hz, or 3 MHz Bitclock (.333us/sample)
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// Measured on scope : 4 bitclock-ticks every 1200ns --> 300ns bitclock ???
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// 12000000L/(div*bestbck*2)
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#define WS_I2S_BCK (17)
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#define WS_I2S_DIV (4)
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#define NUM_I2S_ZERO_BYTES (28) // WS2812 LED Treset = 67us (must be >50us)
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#define NUM_I2S_ZERO_WORDS (NUM_I2S_ZERO_BYTES / 4)
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// -----------------------------------------------------
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#ifndef i2c_bbpll
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#define i2c_bbpll 0x67
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#define i2c_bbpll_en_audio_clock_out 4
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#define i2c_bbpll_en_audio_clock_out_msb 7
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#define i2c_bbpll_en_audio_clock_out_lsb 7
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#define i2c_bbpll_hostid 4
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#endif
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// -----------------------------------------------------
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#define i2c_writeReg_Mask(block, host_id, reg_add, Msb, Lsb, indata) rom_i2c_writeReg_Mask(block, host_id, reg_add, Msb, Lsb, indata)
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#define i2c_readReg_Mask(block, host_id, reg_add, Msb, Lsb) rom_i2c_readReg_Mask(block, host_id, reg_add, Msb, Lsb)
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#define i2c_writeReg_Mask_def(block, reg_add, indata) i2c_writeReg_Mask(block, block##_hostid, reg_add, reg_add##_msb, reg_add##_lsb, indata)
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#define i2c_readReg_Mask_def(block, reg_add) i2c_readReg_Mask(block, block##_hostid, reg_add, reg_add##_msb, reg_add##_lsb)
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// -----------------------------------------------------
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#ifndef ETS_SLC_INUM
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#define ETS_SLC_INUM 1
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#endif
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// -----------------------------------------------------
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// from i2s_reg.h
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#define DR_REG_I2S_BASE (0x60000e00)
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#define I2STXFIFO (DR_REG_I2S_BASE + 0x0000)
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#define I2SRXFIFO (DR_REG_I2S_BASE + 0x0004)
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#define I2SCONF (DR_REG_I2S_BASE + 0x0008)
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#define I2S_BCK_DIV_NUM 0x0000003F
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#define I2S_BCK_DIV_NUM_S 22
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#define I2S_CLKM_DIV_NUM 0x0000003F
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#define I2S_CLKM_DIV_NUM_S 16
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#define I2S_BITS_MOD 0x0000000F
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#define I2S_BITS_MOD_S 12
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#define I2S_RECE_MSB_SHIFT (BIT(11))
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#define I2S_TRANS_MSB_SHIFT (BIT(10))
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#define I2S_I2S_RX_START (BIT(9))
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#define I2S_I2S_TX_START (BIT(8))
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#define I2S_MSB_RIGHT (BIT(7))
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#define I2S_RIGHT_FIRST (BIT(6))
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#define I2S_RECE_SLAVE_MOD (BIT(5))
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#define I2S_TRANS_SLAVE_MOD (BIT(4))
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#define I2S_I2S_RX_FIFO_RESET (BIT(3))
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#define I2S_I2S_TX_FIFO_RESET (BIT(2))
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#define I2S_I2S_RX_RESET (BIT(1))
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#define I2S_I2S_TX_RESET (BIT(0))
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#define I2S_I2S_RESET_MASK 0xf
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#define I2SINT_RAW (DR_REG_I2S_BASE + 0x000c)
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#define I2S_I2S_TX_REMPTY_INT_RAW (BIT(5))
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#define I2S_I2S_TX_WFULL_INT_RAW (BIT(4))
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#define I2S_I2S_RX_REMPTY_INT_RAW (BIT(3))
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#define I2S_I2S_RX_WFULL_INT_RAW (BIT(2))
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#define I2S_I2S_TX_PUT_DATA_INT_RAW (BIT(1))
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#define I2S_I2S_RX_TAKE_DATA_INT_RAW (BIT(0))
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#define I2SINT_ST (DR_REG_I2S_BASE + 0x0010)
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#define I2S_I2S_TX_REMPTY_INT_ST (BIT(5))
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#define I2S_I2S_TX_WFULL_INT_ST (BIT(4))
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#define I2S_I2S_RX_REMPTY_INT_ST (BIT(3))
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#define I2S_I2S_RX_WFULL_INT_ST (BIT(2))
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#define I2S_I2S_TX_PUT_DATA_INT_ST (BIT(1))
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#define I2S_I2S_RX_TAKE_DATA_INT_ST (BIT(0))
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#define I2SINT_ENA (DR_REG_I2S_BASE + 0x0014)
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#define I2S_I2S_TX_REMPTY_INT_ENA (BIT(5))
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#define I2S_I2S_TX_WFULL_INT_ENA (BIT(4))
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#define I2S_I2S_RX_REMPTY_INT_ENA (BIT(3))
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#define I2S_I2S_RX_WFULL_INT_ENA (BIT(2))
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#define I2S_I2S_TX_PUT_DATA_INT_ENA (BIT(1))
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#define I2S_I2S_RX_TAKE_DATA_INT_ENA (BIT(0))
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#define I2SINT_CLR (DR_REG_I2S_BASE + 0x0018)
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#define I2S_I2S_TX_REMPTY_INT_CLR (BIT(5))
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#define I2S_I2S_TX_WFULL_INT_CLR (BIT(4))
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#define I2S_I2S_RX_REMPTY_INT_CLR (BIT(3))
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#define I2S_I2S_RX_WFULL_INT_CLR (BIT(2))
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#define I2S_I2S_PUT_DATA_INT_CLR (BIT(1))
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#define I2S_I2S_TAKE_DATA_INT_CLR (BIT(0))
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#define I2STIMING (DR_REG_I2S_BASE + 0x001c)
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#define I2S_TRANS_BCK_IN_INV (BIT(22))
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#define I2S_RECE_DSYNC_SW (BIT(21))
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#define I2S_TRANS_DSYNC_SW (BIT(20))
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#define I2S_RECE_BCK_OUT_DELAY 0x00000003
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#define I2S_RECE_BCK_OUT_DELAY_S 18
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#define I2S_RECE_WS_OUT_DELAY 0x00000003
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#define I2S_RECE_WS_OUT_DELAY_S 16
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#define I2S_TRANS_SD_OUT_DELAY 0x00000003
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#define I2S_TRANS_SD_OUT_DELAY_S 14
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#define I2S_TRANS_WS_OUT_DELAY 0x00000003
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#define I2S_TRANS_WS_OUT_DELAY_S 12
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#define I2S_TRANS_BCK_OUT_DELAY 0x00000003
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#define I2S_TRANS_BCK_OUT_DELAY_S 10
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#define I2S_RECE_SD_IN_DELAY 0x00000003
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#define I2S_RECE_SD_IN_DELAY_S 8
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#define I2S_RECE_WS_IN_DELAY 0x00000003
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#define I2S_RECE_WS_IN_DELAY_S 6
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#define I2S_RECE_BCK_IN_DELAY 0x00000003
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#define I2S_RECE_BCK_IN_DELAY_S 4
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#define I2S_TRANS_WS_IN_DELAY 0x00000003
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#define I2S_TRANS_WS_IN_DELAY_S 2
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#define I2S_TRANS_BCK_IN_DELAY 0x00000003
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#define I2S_TRANS_BCK_IN_DELAY_S 0
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#define I2S_FIFO_CONF (DR_REG_I2S_BASE + 0x0020)
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#define I2S_I2S_RX_FIFO_MOD 0x00000007
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#define I2S_I2S_RX_FIFO_MOD_S 16
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#define I2S_I2S_TX_FIFO_MOD 0x00000007
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#define I2S_I2S_TX_FIFO_MOD_S 13
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#define I2S_I2S_DSCR_EN (BIT(12))
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#define I2S_I2S_TX_DATA_NUM 0x0000003F
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#define I2S_I2S_TX_DATA_NUM_S 6
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#define I2S_I2S_RX_DATA_NUM 0x0000003F
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#define I2S_I2S_RX_DATA_NUM_S 0
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#define I2SRXEOF_NUM (DR_REG_I2S_BASE + 0x0024)
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#define I2S_I2S_RX_EOF_NUM 0xFFFFFFFF
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#define I2S_I2S_RX_EOF_NUM_S 0
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#define I2SCONF_SIGLE_DATA (DR_REG_I2S_BASE + 0x0028)
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#define I2S_I2S_SIGLE_DATA 0xFFFFFFFF
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#define I2S_I2S_SIGLE_DATA_S 0
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#define I2SCONF_CHAN (DR_REG_I2S_BASE + 0x002c)
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#define I2S_RX_CHAN_MOD 0x00000003
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#define I2S_RX_CHAN_MOD_S 3
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#define I2S_TX_CHAN_MOD 0x00000007
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#define I2S_TX_CHAN_MOD_S 0
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// -----------------------------------------------------
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#endif
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// end of file
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